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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD605 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual, low noise, single-supply variable gain amplifier functional block diagram precision passive input attenuator fixed gain amplifier +34.4db differential attenuator 0 to ?8.4db out vocm vgn vref +in ?n gain control and scaling fbk AD605 features two independent linear-in-db channels input noise at maximum gain: 1.8 nv/ hz , 2.7 pa/ hz bandwidth: 40 mhz (C3 db) differential input absolute gain range programmable: C14 db to +34 db (fbk shorted to out), through 0 db to +48 db (fbk open) variable gain scaling: 20 db/v through 40 db/v stable gain with temperature and supply variations single-ended unipolar gain control output common-mode independently set power shutdown at lower end of gain control single 5 v supply low power: 90 mw/channel drives a/d converters directly applications ultrasound and sonar time-gain control high performance agc systems signal measurement product description the AD605 is a low noise, accurate, dual channel, linear-in-db variable gain amplifier, which is optimized for any application requiring high performance, wide bandwidth variable gain con- trol. operating from a single 5 v supply, the AD605 provides differential inputs and unipolar gain control for ease of use. added flexibility is achieved with a user determined gain range and an external reference input which provides user determined gain scaling (db/v). the high performance linear-in-db response of the AD605 is achieved with the differential input, single supply, exponential amplifier (dsx-amp) architecture. each of the dsx-amps comprise a variable attenuator of 0 db to ?8.4 db followed by a high speed fixed gain amplifier. the attenuator is based on a 7-stage r-1.5-r ladder network. the attenuation between tap points is 6.908 db and 48.360 db for the entire ladder network. the dsx-amp architecture results in 1.8 nv/ hz input noise spectral density and will accept a 2.0 v input signal when vocm is biased at vp/2. each independent channel of the AD605 provides a gain range of 48 db which can be optimized for the application. gain ranges between ?4 db to +34 db and 0 db to +48 db can be selected by a single re sistor between pins fbk and out. the lower and upper gain range are determined by shorting pin fbk to out, or leaving pin fbk unconnected respectively. the two channels of the AD605 can be cascaded to provide 96 db of very accurate gain range in a monolithic package. the gain control interface provides an input resistance of approxi- mately 2 m ? and scale factors from 20 db/v to 30 db/v for a vref input voltage of 2.5 v to 1.67 v respectively. note that scale factors up to 40 db are achievable with reduced accuracy for scales above 30 db. the gain scales linearly with control volt- ages (vgn) of 0.4 v to 2.4 v for the 20 db/v scale and 0.20 v to 1.20 v for the 40 db/v scale. when vgn is <50 mv the amplifier is powered-down to draw 1.9 ma. under normal operation, the quiescent supply current of each amplifier chan- nel is only 18 ma. the AD605 is available in a 16-lead plastic dip and soic, and is guaranteed for operation over the ?0 c to +85 c tempera- ture range.
AD605?pecifications C2C rev. b model AD605a AD605b parameter conditions min typ max min typ max unit input characteristics input resistance 175 40 175 40 ? input capacitance 3.0 3.0 pf peak input voltage 2.5 2.5 2.5 2.5 v input voltage noise vgn = 2.9 v 1.8 1.8 nv/ hz input current noise vgn = 2.9 v 2.7 2.7 pa/ hz noise figure r s = 50 ? , f = 10 mhz at minimum gain, 8.4 8.4 db vgn = 2.9 v r s = 200 ? , f = 10 mhz at minimum gain, 12 12 db vgn = 2.9 v common-mode rejection ratio f = 1 mhz, vgn = 2.65 v ?0 ?0 db output characteristics ? db bandwidth constant with gain 40 40 mhz slew rate vgn = 1.5 v, output = 1 v step 170 170 v/ s output signal range r l 500 ? 2.5 1.5 2.5 1.5 v output impedance f = 10 mhz 2 2 ? output short-circuit current 40 40 ma harmonic distortion vgn = 1 v, vout = 1 v p-p, hd2 f = 1 mhz ?4 ?4 dbc hd3 f = 1 mhz ?8 ?8 dbc hd2 f = 10 mhz ?1 ?1 dbc hd3 f = 10 mhz ?3 ?3 dbc two-tone intermodulation r s = 0 ? , vgn = 2.9 v, vout = 1 v p-p distortion (imd) f = 1 mhz ?2 ?2 dbc f = 10 mhz ?0 ?0 dbc 1 db compression point f = 10 mhz, vgn = 2.9 v, output referred +15 +15 dbm third order intercept f = 10 mhz, vgn = 2.9 v, vout = 1 v p-p, ? ? dbm input referred channel-to-channel crosstalk ch1: vgn = 2.65 v, inputs shorted, ?0 ?0 db ch2: vgn = 1.5 v (mid gain), f = 1 mhz, vout = 1 v p-p group delay variation 1 mhz < f < 10 mhz, full gain range 2.0 2.0 ns vocm input resistance 45 45 k ? accuracy absolute gain error ?4 db to ?1 db 0.25 v < vgn < 0.40 v ?.2 +1.0 +3.0 ?.2 +0.75 +3.0 db ?1 db to +29 db 0.40 v < vgn < 2.40 v ?.0 0.3 +1.0 ?.0 0.2 +1.0 db +29 db to +34 db 2.40 v < vgn < 2.65 v ?.5 ?.25 +1.2 ?.5 ?.25 +1.2 db gain scaling error 0.4 v < vgn < 2.4 v 0.25 0.25 db/v output offset voltage vref = 2.500 v, vocm = 2.500 v ?0 30 50 ?0 30 50 mv output offset variation vref = 2.500 v, vocm = 2.500 v 30 95 30 50 mv gain control interface gain scaling factor vref = 2.5 v, 0.4 v < vgn < 2.4 v 19 20 21 19 20 21 db/v vref = 1.67 v 30 30 db/v gain range fbk short to out ?4 ?+34 ?4 ?+34 db fbk open 0 ?+48 0 ?+48 db input voltage (vgn) range 20 db/v, vref = 2.5 v 0.1 ?2.9 0.1 ?2.9 v input bias current ?.4 ?.4 a input resistance 22m ? response time 48 db gain change 0.2 0.2 s power supply power dissipation 90 90 mw vref input resistance 10 10 k ? quiescent supply current vpos 18 23 18 23 ma power down vpos, vgn < 50 mv 1.9 3.0 1.9 3.0 ma power-up response time 48 db gain, v out = 2 v p-p 0.6 0.6 s power-down response time 0.4 0.4 s (each channel at t a = 25 c, v s = 5 v, r s = 50 , r l = 500 , c l = 5 pf, vref = 2.5 v (scaling = 20 db/v), ?4 db to +34 db gain range, unless otherwise noted.)
AD605 C3C rev. b absolute maximum ratings * supply voltage +v s pins 12, 13 (with pins 4, 5 = 0 v) . . . . . . . . . . . . . . . 6.5 v input voltages pins 1?, 6?, 16 . . . . . . . . . . . . . . . vpos, 0 internal power dissipation plastic (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 w small outline (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 w operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering 60 seconds . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option ja AD605an ?0 c to +85 c plastic dip n-16 85 c/w AD605ar ?0 c to +85 c small outline ic (soic) r-16a 100 c/w AD605bn ?0 c to +85 c plastic dip n-16 85 c/w AD605br ?0 c to +85 c small outline ic (soic) r-16a 100 c/w AD605achips die AD605ar-reel 13" reel AD605ar-reel7 7" reel AD605br-reel 13" reel AD605br-reel7 7" reel AD605-eb evaluation board pin function descriptions 16-lead package for dual channel AD605 pin no. mnemonic description 1 vgn1 ch1 gain-control input and power-down pin. if grounded, device is off, otherwise positive voltage increases gain. 2 in1 ch1 negative input. 3 +in1 ch1 positive input. 4 gnd1 ground. 5 gnd2 ground. 6 +in2 ch2 positive input. 7 in2 ch2 negative input. 8 vgn2 ch2 gain-control input and power-down pin. if grounded, device is off, otherwise positive voltage increases gain. 9 vocm input to this pin defines common-mode voltage for out1 and out2. 10 out2 ch2 output. 11 fbk2 feedback pin that selects gain range of ch2. 12 vpos positive supply. 13 vpos positive supply. 14 fbk1 feedback pin that selects gain range of ch1. 15 out1 ch1 output. 16 vref input to this pin sets gain-scaling for both channels: 2.5 v = 20 db/v, 1.67 v = 30 db/v. pin configuration 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD605 vgn1 vpos fbk1 out1 vref in1 +in1 gnd1 out2 fbk2 vpos gnd2 +in2 in2 vgn2 vocm caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD605 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
vgn volts gain db 40 20 0.1 0.5 2.9 0.9 1.3 1.7 2.1 2.5 30 20 10 0 10 40 c, +25 c, +85 c tpc 1. gain vs. vgn v ref volts gain scaling dbv 40.0 37.5 20.0 1.25 1.50 2.50 1.75 2.00 2.25 30.0 27.5 25.0 22.5 35.0 32.5 theoretical actual tpc 4. gain scaling vs. v ref vgn volts gain error db 2.0 1.5 2.0 0.2 0.7 2.7 1.2 1.7 2.2 0.0 0.5 1.0 1.5 1.0 0.5 20db/v v ref = 2.50v 30db/v v ref = 1.67v tpc 7. gain error vs. vgn for different gain scalings vgn volts gain db 50 20 0.1 0.5 2.9 0.9 1.3 1.7 2.1 2.5 40 20 10 0 10 30 fbk (open) fbk (short) tpc 2. gain vs. vgn for different gain ranges vgn volts gain error db 3.0 2.5 3.0 0.2 0.7 2.7 1.2 1.7 2.2 1.0 1.5 2.0 2.5 2.0 1.0 1.5 0.5 0.5 0.0 40 c +85 c +25 c tpc 5. gain error vs. vgn at different temperatures delta gain db percentage 20 6 0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 18 8 4 2 16 12 14 10 0.6 0.8 g(db) = g(ch1) g(ch2) n = 50 tpc 8. gain match, vgn1 = vgn2 = 1.0 v (v ref = 2.5 v (20 db/v scaling), f = 1 mhz, r l = 500 , c l = 5 pf, t a = 25 c, v ss = 5 v) AD605 typical performance characteristics (per channel) C4C rev. b vgn volts gain db 40 20 0.1 0.5 2.9 0.9 1.3 1.7 2.1 2.5 30 20 10 0 10 30db/v (v ref = 1.67v) 20db/v (v ref = 2.50v) actual actual tpc 3. gain vs. vgn for different gain scalings vgn volts gain error db 2.0 1.5 2.0 0.2 0.7 2.7 1.2 1.7 2.2 0.0 0.5 1.0 1.5 1.0 0.5 f = 1mhz f = 5mhz f = 10mhz tpc 6. gain error vs. vgn at different frequencies delta gain db percentage 20 6 0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 0.8 18 8 4 2 16 12 14 10 g(db) = g(ch1) g(ch2) n = 50 tpc 9. gain match, vgn1 = vgn2 = 2.50 v
AD605 C5C rev. b frequency hz gain db 60 40 60 100k 1m 100m 10m 0 20 40 20 vgn = 2.9v (fbk = open) vgn = 2.9v (fbk = short) vgn = 1.5v (fbk = open) vgn = 1.5v (fbk = short) vgn = 0.1v (fbk = open) vgn = 0.1v (fbk = short) vgn = 0.0v tpc 10. ac response vgn volts 1000 100 1 0.1 0.5 2.1 10 0.9 1.3 1.7 2.5 2.9 noise nv/ hz tpc 13. input referred noise vs. vgn frequency 100 10 0.1 110 1k 100 1 vgn = 2.9v r source alone noise nv/ hz tpc 16. input referred noise vs. r source vgn volts v os volts 2.525 2.475 0 0.5 3.0 1.0 1.5 2.0 2.5 2.520 2.495 2.490 2.485 2.480 2.515 2.510 2.500 2.505 v ocm = 2.50v 40 c +25 c +85 c tpc 11. output offset vs. vgn temperature c 2.00 1.75 1.60 40 90 200 20406080 1.95 1.80 1.70 1.65 1.90 1.85 vgn = 2.9v noise nv/ hz tpc 14. input referred noise vs. temperature r source noise figure db 30 25 5 110 1k 100 15 10 20 vgn = 2.9v tpc 17. noise tpc vs. r source vgn volts 130 90 125 110 105 100 95 120 115 0 0.5 3.0 1.0 1.5 2.0 2.5 +85 c +25 c 40 c noise nv/ hz tpc 12. output referred noise vs. vgn frequency hz 1.90 1.85 1.60 100k 1m 10m 1.80 1.75 1.70 1.65 vgn = 2.9v noise nv/ hz tpc 15. input referred noise vs. frequency vgn volts noise figure db 60 0 0.1 0.5 2.9 0.9 1.3 1.7 2.1 2.5 50 40 30 20 10 r s = 50 tpc 18. noise tpc vs. vgn
AD605 C6C rev. b frequency hz harmonic distortion dbc 30 35 70 100k 1m 100m 10m 50 55 65 60 40 45 v o = 1v p-p vgn = 1.0v hd2 hd3 tpc 19. harmonic distortion vs. frequency vgn volts p in dbm 15 20 0.1 0.5 2.9 0.9 1.3 1.7 2.1 2.5 10 0 5 10 15 5 freq = 10mhz freq = 1mhz input generator limit tpc 22. 1 db compression vs. vgn 100ns / div 40mv / div v o = 200mv p-p vgn = 1.5v 200 200 253ns 1.253 s trig'd tpc 25. small signal pulse response vgn volts 0.5 0.8 2.9 1.1 1.4 1.7 2.0 2.3 2.6 harmonic distortion dbc 35 75 55 60 65 70 40 50 45 hd3 (10mhz) hd2 (10mhz) hd2 (1mhz) hd3 (1mhz) tpc 20. harmonic distortion vs. vgn vgn volts intercept dbm 35 5 30 15 10 5 0 25 20 0.6 1 3 1.4 1.8 2.2 2.6 v o = 1v p-p f = 1mhz f = 10mhz tpc 23. third order intercept vs. vgn vgn volts 2.9v 0.0v 10 0% 100 90 500mv 200ns 500mv tpc 26. power-up/down response frequency mhz p out dbm 20 90 120 9.92 9.96 10 10.02 10.04 30 80 100 110 60 70 40 50 f = 10mhz v o = 1v p-p vgn = 1.0v tpc 21. intermodulation distortion 100ns / div 400mv / div v o = 2v p-p vgn = 1.5v 2v 2v 253ns 1.253 s tpc 24. large signal pulse response vgn volts 2.9v 0.1v 10 0% 100 90 500mv 100ns 500mv tpc 27. gain response
AD605 C7C rev. b frequency hz crosstalk db 30 40 90 100k 1m 100m 10m 50 60 80 70 vgn1 = 1v v out1 = 1v p-p v in2 = gnd vgn2 = 2.9v vgn2 = 2.5v vgn2 = 2.0v vgn2 = 0.1v tpc 28. crosstalk (ch1 to ch2) vs. frequency temperature c supply current ma 25 20 0 40 90 20 0 20 40 60 80 15 10 5 +i s (AD605) +i s (vgn = 0) tpc 31. supply current (one channel) vs. temperature frequency hz 0 10 60 100k 1m 100m 10m 20 30 50 40 cmrr db v in = 0dbm vgn = 2.9v vgn = 2.5v vgn = 2.0v vgn = 0.1v tpc 29. common-mode rejection vs. frequency frequency hz input impedance 180 175 140 100k 1m 100m 10m 160 155 145 150 170 165 vgn = 2.9v tpc 30. input impedance vs. frequency frequency hz 16 14 4 100k 1m 100m 10m 12 10 6 8 delay ns vgn = 0.1v vgn = 2.9v tpc 32. group delay vs. frequency
AD605 C8C rev. b theory of operation the AD605 is a dual channel, low noise variable gain amplifier. figure 1 shows the simplified block diagram of one channel. each channel consists of a single-supply x-amp (hereafter called dsx, differential single-supply x-amp) made up of: (a) a precision passive attenuator (differential ladder) (b) a gain control block (c) a vocm buffer with supply splitting resistors r3 and r4 (d) an active feedback amplifier 1 (afa) with gain setting resistors r1 and r2. the linear-in-db gain response of the AD605 can generally be described by equation 1: g ( db ) = ( gain scaling ( db/v )) ( gain control ( v )) (19 db ?(14 db ) ( fb )) (1) where fb = 0 if fbk-to-out are shorted, fb = 1 if fbk-to-out is open. each channel provides between ?4 db to +34.4 db through 0 db to +48.4 db of gain depending on the value of the resistance connected between pin fbk and out. the center 40 db of gain is exactly linear-in-db while the gain error increases at the top and bottom of the range. the gain is set by the gain control voltage (vgn). the vref input establishes the gain scaling the useful gain scaling range is between 20 db/v and 40 db/v for a vref voltage of 2.5 v and 1.25 v respectively. for example, if fbk to out were shorted and vref were set to 2.50 v (to establish a gain scaling of 20 db/v), the gain equation would simplify to: g ( db ) = (20 ( db/v )) ( vgn ( v )) ?19 db (2) the desired gain can then be achieved by setting the unipolar gain control (vgn) to a voltage within its nominal operating range of 0.25 v to 2.65 v (for 20 db/v gain scaling). the gain is monotonic for a complete gain control range of 0.1 v to 2.9 v. maximum gain can be achieved at a vgn of 2.9 v. since the two channels are identical, only channel 1 will be used to describe their operation. vref and vocm are the only inputs that are shared by the two channels, and s ince they are normally ac grounds, crosstalk between the two channels is minimized. for highest gain scaling accuracy, vref should have an external low impedance voltage source. for low accu- racy 20 db/v applications, the vref input can be decoupled with a capacitor to ground. in this mode the gain scaling will be 1 to understand the active-feedback amplifier topology, refer to the ad830 data sheet. the ad830 is a practical implementation of the idea. determined by the midpoint between +vcc and gnd, so care should be taken to control the supply voltage to 5 v. the input resistance looking into the vref pin is 10 k ? 20%. the AD605 is a single-supply circuit and the vocm pin is used to establish the dc level of the midpoint of this portion of the circuit. vocm needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 v, gnd); however if the dc level of the output is important to the user (see applications section for ad9050 example), then vocm can be specifically set. the input resistance looking into the vocm pin is 45 k ? 20%. differential ladder (attenuator) the attenuator before the fixed gain amplifier is realized by a differential seven-stage r?.5r resistive ladder network with an untrimmed input resistance of 175 ? single-ended or 350 ? differentially. the signal applied at the input of the ladder network (figure 2) is attenuated by 6.908 db per tap; thus, the attenuation at the first tap is 6.908 db, at the second, 13.816 db, and so on all the way to the last tap where the attenuation is 48.356 db. a unique circuit technique is used to interpolate continuously between the tap points, thereby providing continu- ous attenuation from 0 db to ?8.36 db. one can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer. since the dsx is a single-supply circuit, some means of biasing its inputs must be provided. node mid together with the vocm buffer performs this function. without internal biasing, external biasing would be required. if not done carefully, the biasing network can introduce additional noise and offsets. by providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the dsx. it should be made clear again that the input to the dsx is still fully differen- tial if driven differentially, i.e., pins +in and ?n see the same signal but with opposite polarity. what changes is the load as seen by the driver; it is 175 ? when each input is driven single- ended, but 350 ? when driven differentially. this can be easily explained when thinking of the ladder network as just two 175 ? resistors connected back-to-back with the middle node, mid, being biased by the vocm buffer. a differential signal applied between nodes +in and ?n will result in zero current into node mid, but a single-ended signal applied to either input +in or ?n while the other input is ac grounded will cause the current delivered by the source to flow into the vocm buffer via node mid. r1 820 vref vgn vpos vocm r3 200k c3 out distributed g m 175 175 g1 gain control ao g2 r2 20 r4 200k ext +in in fbk 3.36k differential attenuator ext c2 c1 figure 1. simplified block diagram of a single channel of the AD605
AD605 C9C rev. b from these equations one can see that all gain curves intercept at the same ?9 db point; this intercept will be 14 db higher (? db) if the fbk to out connection is left open. outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 db of range. for a given gain scaling one can calculate v ref as shown in equa- tion (6). v ref = 2.500 v 20 db / v gain scale (6) 35 30 25 20 15 10 5 0 5 10 15 20 gain db 40db/v 30db/v 20db/v linear-in-db range of AD605 1.0 0.5 1.5 2.0 2.5 3.0 gain control voltage figure 3. ideal gain curves vs. v ref usable gain control voltage ranges are 0.1 v to 2.9 v for 20 db/v scale and 0.1 v to 1.45 v for the 40 db/v scale. vgn voltages of less than 0.1 v are not used for gain-control since below 50 mv the channel is powered down. this can be used to con- serve power and at the same time gate-off the signal. the supply current for a powered-down channel is 1.9 ma, the response time to power the device on-or-off, is less than 1 s. active feedback amplifier (fixed gain amp) to achieve single supply operation and a fully differential input to the dsx, an active-feedback amplifier (afa) was utilized. the afa is basically an op amp with two g m stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. note that the differential input is an open-loop g m stage which requires that it be highly linear over the expected input signal range. in this design, the g m stage that senses the voltages on the attenuator is a distributed one, for example, there are as many g m stages as there are taps on the ladder network. only a few of them are on at any one time, depending on the gain-control voltage. r 6.908db r 1.5r 1.5r r r 13.82db r 1.5r 1.5r r 20.72db r 1.5r 1.5r r 27.63db r 1.5r 1.5r r 34.54db r 1.5r 1.5r r 41.45db r 1.5r 1.5r r 48.36db 1.5r 1.5r 175 175 +in mid in note: r = 96 1.5r = 144 figure 2. rC1.5r dual ladder network one feature of the x-amp architecture is that the output referred noise is constant versus gain over most of the gain range. this can be easily explained by looking at figure 2 and obs erving that the tap resistance is equal for all taps after only a few taps away from the inputs. the resistance seen looking into each tap is 54.4 ? which makes 0.95 nv/ hz of johnson noise spectral density. since there are two attenuators, the overall noise contribution of the ladder network is 2 times 0.95 nv/ hz or 1.34 nv/ hz , a large fraction of the total dsx noise. the rest of the dsx circuit components contribute another 1.20 nv/ hz which together with the attenuator produces 1.8 nv/ hz of total dsx input referred noise. ac coupling as already mentioned, the dsx is a single single-supply circuit and therefore its inputs need to be ac coupled to accommodate ground-based signals. external capacitors c1 and c2 in figure 1 level shift the input signal from ground to the dc value established by vocm (nominal 2.5 v). c1 and c2, together w ith the 175 ? looking into each of dsx inputs (+in and in), will act as high-pass filters with corner frequencies depending on the values chosen for c1 and c2. for example, if c1 and c2 are 0.1 f, then together with the 175 ? input resistance seen into each side of the differential ladder of the dsx, a 3 db high-pass corner at 9.1 khz is formed. if the dsx output needs to be ground referenced, then another ac coupling capacitor will be required for level shifting. this capacitor will also eliminate any dc offsets contributed by the dsx. with a nominal load of 500 ? and a 0.1 f coupling capacitor, this adds a high-pass filter with 3 db corner fre- quency at about 3.2 khz. the choice for all three of these coupling capacitors depends on the application. they should allow the signals of interest to pass unattenuated, while at the same time they can be used to limit the low frequency noise in the system. gain control interface the gain-control interface provides an input resistance of approxim ately 2 m ? at pin vgn1 and gain scaling factors from 20 db/v to 40 db/v for vref input voltages of 2.5 v to 1.25 v r espectively. the gain varies linearly-in-db for the center 40 db of gain range, that is for vgn equal to 0.4 v to 2.4 v for the 20 db/v scale, and 0.25 v to 1.25 v for the 40 db/v scale. figure 3 shows the ideal gain curves when the fbk to out connection is shorted which are described by the fol- lowing equations: g (20 db/v ) = 20 vgn ? 19 , vref = 2.500 v (3) g (30 db/v ) = 30 vgn ? 19 , vref = 1.6666 v (4) g (40 db/v ) = 40 vgn ? 19 , vref = 1.250 v (5)
AD605 C10C rev. b the afa makes a differential input structure possible since one of its inputs (g1) is fully differential; this input is made up of a distributed gm stage. the second input (g2) is used for feed- back. the output of g1 will be some function of the voltages sensed on the attenuator taps which is applied to a high-gain amplifier (a0). because of negative feedback, the differential input to the high-gain amplifier has to be zero, this in turn implies that the differential input voltage to g2 times g m2 (the transcon- ductance of g2) has to be equal to the differential input voltage to g1 times g m1 (the transconductance of g1). therefore the overall gain function of the afa is v out v atten = gm 1 gm 2 r 1 r 2 r 2 (7) where v out is the output voltage, v atten is the effective voltage sensed on the attenuator, (r1 + r2)/r2 = 42, and g m1 /g m2 = 1.25; the overall gain is thus 52.5 (34.4 db). the afa has additional features: (1) inverting the output signal by switching the positive and negative input to the ladder network, (2) the poss ibility of using the in input as a second signal input, and (3) independent control of the dsx co mmon-mode voltage. under normal operating conditions it is best to just connect a decoupling capacitor to pin vocm in which case the common- mode voltage of the dsx is half the supply voltage; this al lows for maximum signal swing. nevert heless, the common- mode voltage can be shifted up or down by directly applying a voltage to vocm. it can also be used as another signal input, the only limitation being the rather low slew rate of the vocm buffer. if the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the dsx; again this is done for level shifting and to eliminate any dc offsets contrib- uted by the dsx (see ac coupling section). the gain range of the dsx is programmable by a resistor con- nected between pins fbk and out. the possible ranges go from 14 db to +34.4 db when the pins are shorted together, to 0 db to +48.4 db when fbk is left open. note that for the higher gain range, the bandwidth of the amplifier is reduced by a factor of five to about 8 mhz since the gain increased by 14 db. this is the case for any constant gain-bandwidth-product amplifier of which the active feedback amplifier is one. applications the most basic circuit in figure 4 shows the conn ections for one channel of the AD605 with a gain range of 14 db to +34.4 db. the signal is applied at pin 3. the ac coupling capaci tors before pins in1 and +in1 should be selected according to the re quired lower cutoff frequency. in this example the 0.1 f capacitors together with the 175 ? seen into each of the dsx input pins provides a 3 db high pass corner of about 9.1 khz. the upper cutoff frequency is determined by the amplifier and is 40 mhz. 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 vref gnd1 +in1 in1 vgn1 out1 fbk1 vpos in2 +in2 gnd2 vpos fbk2 out2 vocm vgn2 AD605 0.1 f 0.1 f vgn v in 0.1 f 5v 0.1 f out 2.500v figure 4. basic connections for a single channel as shown here, the output is ac coupled for optimum perfor- mance. in the case of connecting to the 10-bit 40 msps a/d converter ad9050, ac coupling can be eliminated as long as pin vocm is biased by the same 3.3 v common-mode voltage as the ad9050. pin vref requires a voltage of 1.25 v to 2.5 v, w ith between 40 db/v and 20 db/v gain scaling respect ively. voltage vgn controls the gain; its nominal operating range is from 0.25 v to 2.65 v for 20 db/v gain scaling, and 0.125 v to 1.325 v for 40 db/v scaling. when this pin is taken to ground, the channel will power down and disable its output. connecting two amplifiers to double the gain range figure 5 shows the two channels of the AD605 connected in series to provide a total gain range of 96.8 db. when r1 and r2 are shorts, the gain range will be from 28 db to +68.8 db with a slightly reduced bandwidth of about 30 mhz. the reduction in bandwidth is due to two identical low-pass circuits being connected in series; in the case of two identical single-pole low- pass filters, the bandwidth would be reduced by exactly 2 . if r1 and r2 are replaced by open circuits, i.e., pins fbk1 and fbk2 are left unconnected, then the gain range will shift up by 28 db to 0 db to +96.8 db. as already pointed out earlier, the bandwidth of each individual channel will be reduced by a factor of 5 to about 8 mhz since the gain increased by 14 db. in addition, there is still the 2 reduction because of the series connection of the two channels which results in a final band- width of the higher gain version of about 6 mhz. 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 vref gnd1 +in1 in1 vgn1 out1 fbk1 vpos in2 +in2 gnd2 vpos fbk2 out2 vocm vgn2 AD605 c2 0.1 f vgn v in r1 5v out 2.500v c1 0.1 f c3 0.1 f c4 0.1 f c6 0.1 f r2 c5 0.1 f figure 5. doubling the gain range with two amplifiers
AD605 C11C rev. b two other easy combinations are possible to provide a gain range of 14 db to +82.8 db: (1) make r1 a short and r2 an open, or (2) make r1 an open and r2 a short. the bandwidth for both of these cases will be dominated by the channel that is set to the higher gain and will be about 8 mhz. from a noise standpoint, choice (2) is the better one since by increasing the gain of the first amplifier, the second amplifier s noise will have less of an impact on the total output noise. one further observa- tion regarding noise is that by increasing the gain the output noise will increase proportionally; therefore, there is no increase in signal-to-noise ratio. it will actually stay fixed. it should be noted that by selecting the appropriate values of r1 and r2, any gain range between 28 db to +68.8 db and 0 db to +96.8 db can be achieved with the circuit in figure 5. when using any value other than shorts and opens for r1 and r2, the final value of the gain range will depend on external resistors matching on-chip resistors. since the internal resistors can vary by as much as 20%, the actual values for a particular gain have to be determined empirically. note that the two channels within one part will match quite well; therefore, r1 will track r2 in figure 5. c3 is not required since the common-mode voltage at pin out1 should be identical to the one at pins +in2 and in2, but since only 1 mv of offset at the output of the first dsx will introduce an offset of 53 mv when the second dsx is set to the maximum gain of the lowest gain range (34.4 db), and 263 mv when set to the maximum gain of the highest gain range (48.4 db), it is important to include ac-coupling to get the maximum dynamic range at the output of the cascaded amplifiers. c5 is necessary if the output signal needs to be referenced to any common-mode level other than half of the supply as is provided by pin out2. figure 6 shows the gain verses vgn for the circuit in figure 5 at 1 mhz and the lowest gain range ( 14 db to +34.4 db). note that the gain scaling is 40 db/v, double the 20 db/v of an indi- vidual dsx; this is the result of the parallel connection of the gain control inputs, vgn1 and vgn2. one could of course also sequentially increase the gain by first increasing the gain of channel 1 and then channel 2. in that case vgn1 and vgn2 will have to be driven from separate voltage sources, for instance two separate dacs. f igure 7 shows the gain er ror of figure 6. vgn volts gain db 80 40 0.1 0.5 2.9 f = 1mhz theoretical actual 0 0.9 1.3 1.7 2.1 2.5 70 20 10 20 30 50 30 60 40 10 figure 6. gain vs. vgn for the circuit in figure 5 vgn volts gain error db 4 3 4 0.2 0.7 2.7 1.2 1.7 2.2 0 1 2 3 2 1 f = 1mhz figure 7. gain error vs. vgn for the circuit in figure 5
AD605 C12C rev. b outline dimensions dimensions shown in inches and (mm). c00541C0C5/01(b) printed in u.s.a. 16-lead plastic dip (n-16) 16 18 9 pin 1 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 16-lead small outline ic (r-16a) 16 9 8 1 0.1574 (4.00) 0.1497 (3.80) 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) bsc pin 1 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19)

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